Description

Features

• Complete device family with logic densities of 300 to 900 usable gates
• Device erasure and reprogramming with non-volatile EPROM configuration elements
• Fast pin-to-pin logic delays as low as 10 ns and counter frequencies as high as 100 MHz
• 24 to 68 pins available in dual in-line package (DIP).
• Programmable security bit for protection of proprietary designs
• 100% generically tested to provide 100 % programming yield
• Programmable registers providing D, T, JK, and SR flip flops with individual clear and clock controls